The cells are made from a 2-XNOR gate and a 2-XOR gate. The <SPAN CLASS="boldred">a</SPAN> and <SPAN CLASS="boldred">b</SPAN> inputs are xnored and input to a 2-XOR gate with input <SPAN CLASS="boldred">c</SPAN>. Inputs <SPAN CLASS="boldred">a</SPAN> and <SPAN CLASS="boldred">b</SPAN> have 2 to 4 stage delays, and input <SPAN CLASS="boldred">c</SPAN> has 1 or 2 stage delays. The xnr3v1x05 is made from an xnr2v0x05 and xor2v0x05; the xnr3v1x1 from an xnr2v0x1 and xor2v0x1; the xnr3v1x2 from an xnr2v0x1 and xor2v0x2.<BR>
This configuration is faster and smaller than making the function with 3 series P and N transistors driving the output. The delay shown is from pin <SPAN CLASS="boldred">b</SPAN>, while pin <SPAN CLASS="boldred">c</SPAN> is the fastest input.
