4 XOR gates with 2-OR gate input designed for minimum transistor count and hence smallest size.  The OR gate is made by changing the inverter on the <SPAN CLASS="boldred">a</SPAN> input of a 2-XOR gate into a 2-NOR gate. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.