File flow.txt will run synthesis, logic simulation, place and route,
LVS, DRC and creation of CIF and GDS files.

The vasy, boom, boog and loon synthesis steps are all looped to
try to find the fastest netlist.

vasy produces two netlists, coming from two different sets of
     parameters.
boom produces in excess of 200 netlists.
boog produces around 50 netlists which have different critical
     path delays. Boog only considers the minimum drive strength
     cells.
loon speeds up each of the netlists by optimising in turn with
     0fF and 6fF wireload libraries until no more improvement is
     possible. This step is quite slow, so a time limit has been
     set. The input netlists from boog have been sorted so that
     the fastest ones are optimised first.

Custom versions of the place and route software are needed. The
feedthru cell support in the placer has been modified so that
increments are one base unit wide instead of one track.

After routing the netlist, a script adds pieces of metal around the
vias to give a 2 lambda end overlap of metal. This can give DRC errors
to adjacent metal, so a loop runs DRC; adds layout blockages at the
DRC co-ordinates; and reruns the router with these blockages. The loop
continues until there are no more DRC errors.

This means that the layout can be DRC checked with vsc013.rds, which
checks for a 2 lambda via end overlap. The vsc013x.rds file which
checks for a 1 lambda via overlap has to be used on layout directly
written by NERO.

Critical path delay is 544 ps
Area is                575 um^2
Gate count              58
Occupancy               86%
