#!/bin/bash

export OCP=vga_ocp
export NERO=vga_valu3_nero
export PDV=pdv
export DRUC=druc
export COUGAR=cougar
export LVX=lvx
export S2R=s2r

export OCP_WIDEN=pnr_ocp_widen
export WIDE_FEEDTHS=pnr_wide_feedths
export BLOCK_INST=pnr_block_inst
export VIA_OVERLAP=pnr_via_do_overlap
export SIMPLE_BLOCK=pnr_simple_block
export VIA_DRC_BLOCK=pnr_via_drc_block
export STRIP_BLOCKAGES=pnr_strip_old_blockages

export RDS_TECHNO_200=/usr/share/pharosc/etc/vsc200x.rds
export RDS_TECHNO_013=/usr/share/pharosc/etc/vsc013.rds
export TARGET_LIB=/usr/share/pharosc/alliance/cells/vgalib013
export SPI_MODEL=/usr/share/pharosc/etc/spimodel.cfg
export DREAL_TECHNO_200=/usr/share/pharosc/etc/s200.dreal
export GRAAL_TECHNO_200=/usr/share/pharosc/etc/s.graal
export DREAL_TECHNO_013=/usr/share/pharosc/etc/s013.dreal
export GRAAL_TECHNO_013=/usr/share/pharosc/etc/s.graal
export CATAL=VGALIB013

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_TARGET_LIB=$TARGET_LIB
export MBK_SPI_MODEL=$SPI_MODEL
export DREAL_TECHNO_NAME=$DREAL_TECHNO_200
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_200

export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL LOCAL_CATAL
export MBK_CATAL_NAME=LOCAL_CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
$OCP -margin 0.10 -eqmargin -ioc ../adder4 -rows 5 adder4 adder4_p
$BLOCK_INST adder4_p H adder4_bg

export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
export MBK_CATAL_NAME=LOCAL_CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
#
#                 FIRST HORIZONTAL ROUTE
#
nice -10 $NERO -v -2 -L -p adder4_p adder4 adder4
#    o  Allocating grid size [53,56,3].
# o  Routing stats :
#    - routing iterations    := 13907
#    - re-routing iterations := 784
#    - ratio                 := 5.3366%.

sed -i '/zzzblock/ d' adder4.ap
$PDV adder4
#  - ALU2 length  :=       9144  (average length := 127)
#  - ALU3 length  :=       3224  (average length := 104)
#  - Total length :=      12368  (average length := 114)

#  - Total VIA    :=        141
#
#               Fix metal end overlap of VIA
#
$VIA_OVERLAP adder4 H

$SIMPLE_BLOCK adder4 TALU1 big
$SIMPLE_BLOCK adder4 TALU2 small
$SIMPLE_BLOCK adder4 TALU3 small
$SIMPLE_BLOCK adder4 TALU8 big

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATAL_NAME=LOCAL_CATAL
#
#    DRC and use result to set blockages for reroute
#
$DRUC adder4
# 36 errors

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
export MBK_CATAL_NAME=LOCAL_CATAL
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
#
#             Loop NERO until no DRC errors
#
./nero_loop adder4 H
# Loop 1 with 36 errors and 0 blockages
# Loop 2 with 2 errors and 11 blockages
# Loop 3 with 0 errors and 12 blockages
$PDV adder4
#  - ALU2 length  :=       9336  (average length := 48)
#  - ALU3 length  :=       3376  (average length := 43)
#  - Total length :=      12712  (average length := 46)
#  - Total VIA    :=        139

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export RDS_IN=cif
export RDS_OUT=cif
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
#
#                 Extract netlist from layout
#
$COUGAR -v -ac adder4 adder4_lay

export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
#
#                           LVS
#
$LVX vst vst adder4 adder4_lay -f | grep '^***** Netlists' | tee adder4.lvs

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
#
#                   DRC with 0.13um rules
#
$DRUC adder4

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export DREAL_TECHNO_NAME=$DREAL_TECHNO_013
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=.:$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
sed 's/ /usr/share/pharosc/' $CATAL > ${CATAL}_MERGE
export MBK_CATAL_NAME=${CATAL}_MERGE
#
#     Merge the CIF library cells to produce 0.13um layout
#
$S2R -v adder4

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export DREAL_TECHNO_NAME=$DREAL_TECHNO_013
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=gds
export RDS_OUT=gds
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=.:$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
sed 's/ /usr/share/pharosc/' $CATAL > ${CATAL}_MERGE
export MBK_CATAL_NAME=${CATAL}_MERGE
#
#                 Merge the GDS library cells
#
$S2R -v adder4

#
# Check and report the number of DRC and LVS errors
#
echo
for layout in adder4
do
  drc_errors=$(grep -c 'ERROR Code' ${layout}.drc)
  if [ "$drc_errors" -eq 0 ]
  then
    echo "# No DRC errors in "$layout"."
  else
    echo "#! "$layout" has "$drc_errors" DRC errors. Please check."
  fi
  echo -n "# LVS result for "$layout" :"
  cat ${layout}.lvs
done

#export RDS_IN=cif
#export RDS_OUT=cif
#/usr/share/pharosc/bin/l2p -color -drawingsize=725x1068 -noheader -real -rflattentrans -nrfname -niname -nsname -scale=0.5 adder4
