#!/bin/bash

# The layout uses the library with metal-2 mapped to ALU3
# to demonstrate the possibility of metal-1 connections
# between cells which can be seen in adder4_v.ap at (210,350).

# Synthesis loop to find circuit with lowest delay
# with 6fF wireloads
./syn_loop | tee syn_loop.jou

# Simulate behavioural circuit produced from boom
# and gate level circuit produced from loon
bash sim.txt

# Place and route circuit for metal-2 running horizontally
# and vertically; then extract logic netlist from layouts
# and compare to the one produced by loon. Run DRC with
# 2um rules and then merge in CIF and GDS files.
./layout_loop | tee layout_loop.jou
