The script flow.txt is the command sequence for synthesis, simulation,
P&R, DRC, LVS and GDS and CIF file creation.

The script syn_loop is the synthesis part which runs vasy, boom
and boog, then a sequence of loon using the 0fF and 6fF wireload
libraries to provide the final RAM netlist. The goal is to find
the fastest netlist with a 6fF wireload.

A script find_crit_path writes out the critical path for the 0fF and
6fF wireload libraries.

The file sim.txt simulates the ram after the vasy, boom, boog and loon
steps. The vasy simulation result is wrong. I don't know why.

The placement from ocp is modified to insert a two track wide feedthru
cell at the left and right to ensure each cell row is properly
terminated with well and substrate tie downs. A script also merges
adjacent feedthru cells that are wider than 2 tracks.

Routing is done twice, once with metal-2 horizontally and once with
metal-2 vertically.

After routing the netlist, a script adds pieces of metal around the
vias to give a 2 lambda end overlap of metal. This can give DRC errors
to adjacent metal, so a loop runs DRC; adds layout blockages at the
DRC co-ordinates; and reruns the router with these blockages. The loop
continues until there are no more DRC errors.

This means that the layout can be DRC checked with vsc013.rds, which
checks for a 2 lambda via end overlap. The vsc013x.rds file which
checks for a 1 lambda via overlap has to be used on layout directly
written by NERO.

                             0fF     6fF
Critical path delay is  ps  1114    1343
Area is               um^2  1046    1046
Gate count                   168.7   168.7
Occupancy                     84%     84%
